1. Field of the Invention
The present invention relates to a CMOS (complementary metal oxide semiconductor) integrated circuit device.
2. Description of the Prior Art
Recently, CMOSICs have been in increasing demand because of their low power consumption. However, problems arise along with an increase in the packing density of the CMOSIC. In a conventional CMOSIC manufacturing method, a distance between a p-type semiconductor layer as a source or drain of a p-channel transistor and an n-type semiconductor layer as a source or drain of an n-channel transistor tends to be increased in order to prevent a latch-up phenomenon. In other words, a field insulating film or isolation region is formed to have a sufficient width to prevent any latch-up phenomenon.
This problem will be described with reference to FIG. 1. FIG. 1 is a sectional view showing an example of a conventional CMOSIC.
A p-type well region 2 is formed in a major surface of an n-type semiconductor substrate 1. N-type semiconductor layers 4 which have a high impurity concentration (to be referred to as n.sup.+ -type semiconductor layers 4 hereinafter) are formed in a surface of the p-type well region 2. The n.sup.+ -type semiconductor layers 4 respectively correspond to source and drain regions of an n-channel transistor. A gate electrode 5 is deposited on the p-type well region 2 through a gate insulating film 9. P-type semiconductor layers 3 which have a high impurity concentration (to be referred to as p.sup.+ -type semiconductor layers 3 hereinafter) are formed in a surface of a semiconductor element formation region of the n-type semiconductor substrate 1, which region is sited apart from the p-type well region 2. The p.sup.+ -type semiconductor layers 3 correspond to the source and drain regions of a p-channel transistor. A gate electrode 6 is deposited on the n-type semiconductor substrate 1 through a gate insulating film 10. After an insulating film 8 is deposited to cover the entire surface, it is etched to form contact holes for the source and the drain. Metal wiring layers 7 are then deposited on the source and the drain regions to form the source and drain electrodes, respectively. Thus, a CMOSIC is prepared.
A width a as shown in FIG. 1 must be determined to render the effect of an n-channel parasitic transistor negligible. Similarly, a width b as shown in FIG. 1 must be determined to render the effect of a p-channel parasitic transistor negligible. Otherwise, a current flowing through the parasitic transistor continues to flow in the n-type semiconductor substrate 1 or the p-type well region 2, thus resulting in a voltage drop. The voltage drop may cause a start trigger for the latch-up phenomenon. Therefore, a minimum width between the p.sup.+ -type semiconductor layer 3 formed in the n-type semiconductor substrate 1 and the adjacent n.sup.+ -type semiconductor layer 4 formed in the p-type well region 2, that is, (a+b) should be about 10 .mu.m. However, such a wide field insulating film or isolation region prevents the CMOSIC from being miniaturized and results in a major obstacle in semiconductor design and manufacture.